Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high I<inf>ON</inf>/I<inf>OFF</inf> by gate configuration and barrier modulation

Abstract

In this paper, a novel silicon-based T-gate Schottky barrier tunneling FET (TSB-TFET) is proposed and experimentally demonstrated. With enhanced electric field at source side through gate configuration for steeper subthreshold slope (SS), the device with self-depleted structure can effectively suppress the leakage current and simultaneously achieve the dominant Schottky barrier tunneling current for high ON-current without area penalty, which can alleviate the problems in silicon TFET. In addition, the proposed TSB-TFET can have comparable DIBL effect and reduced gate-to-drain capacitance compared with traditional TFET. Further device optimization is experimentally achieved by extended multi-finger gate configuration of the same footprint and barrier modulation by dopant segregation Schottky technology. With compatible bulk CMOS technology, the fabricated device can achieve steep SS over almost 5 decades of current, as well as high I ON /I OFF ratio (∼107). The proposed device with high compatibility is very promising for future low power system applications.