Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode

C.H Lee,D.L Kwong,J.J Lee,R.D Clark,Y Harada,J.H Sim,X Lei,S.H Bae,W.P Bai,M Niwa

doi:10.1109/vlsit.2002.1015398

Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode

C.H Lee, D.L Kwong + Show 8 more

https://doi.org/10.1109/vlsit.2002.1015398

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Publication Date: Jun 11, 2002

Citations: 12

Affiliation: The University of Texas at Austin

#Superior Interface Properties #Superior Electron + Show 8 more

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Abstract

In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.

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