Abstract

Probabilistic graphical models are powerful mathematical formalisms for machine learning and reasoning under uncertainty that are widely used for cognitive computing. However, they cannot be employed efficiently for large problems (with variables in the order of 100K or larger) on conventional systems, due to inefficiencies resulting from layers of abstraction and separation of logic and memory in CMOS implementations. In this paper, we present a magnetoelectric probabilistic technology framework for implementing probabilistic reasoning functions. The technology leverages straintronic magneto-tunneling junction (S-MTJ) devices in a novel mixed-signal circuit framework for direct computations on probabilities while enabling in-memory computations with persistence. Initial evaluations of the Bayesian likelihood estimation operation occurring during Bayesian Network inference indicate up to 127× lower area, 214× lower active power, and 70× lower latency compared to an equivalent 45-nm CMOS Boolean implementation.

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