Abstract

In-plane gate homojunction thin-film transistors (TFTs) with patterned channel are self-assembled on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based solid electrolytes with only one nickel shadow mask. All indium-tin oxide channel and electrodes (source, drain, and gate) are deposited simultaneously by one-step magnetron sputtering, and no alignment is necessary. Such TFTs exhibited a good performance with a low operation voltage of 2.0 V, a large field-effect mobility of 28.7 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s, a low subthreshold swing of 125 mV/decade, and a large on-off ratio of 1.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , respectively. A two-serial-capacitor model for the low-voltage operation mechanism is proposed and discussed.

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