Abstract
Patterning of thin films with lithography techniques for making semiconductor devices has been facing increasing difficulties with feature sizes shrinking to the sub-10 nm range, and alternatives have been actively sought from area-selective thin film deposition processes. Here, an entirely new method is introduced to self-aligned thin-film patterning: area-selective gas-phase etching of polymers. The etching reactions are selective to the materials underneath the polymers. Either O2 or H2 can be used as an etchant gas. After diffusing through the polymer film to the catalytic surfaces, the etchant gas molecules are dissociated into their respective atoms, which then readily react with the polymer, etching it away. On noncatalytic surfaces, the polymer film remains. For example, polyimide and poly(methyl methacrylate) (PMMA) were selectively oxidatively removed at 300 °C from Pt and Ru, while on SiO2 they stayed. CeO2 also showed a clear catalytic effect for the oxidative removal of PMMA. In H2, the most active surfaces catalysing the hydrogenolysis of PMMA were Cu and Ti. The area-selective etching of polyimide from Pt was followed by area-selective atomic layer deposition of iridium using the patterned polymer as a growth-inhibiting layer on SiO2, eventually resulting in dual side-by-side self-aligned formation of metal-on-metal and insulator (polymer)-on-insulator. This demonstrates that when innovatively combined with area-selective thin film deposition and, for example, lift-off patterning processes, self-aligned etching processes will open entirely new possibilities for the fabrication of the most advanced and challenging semiconductor devices.
Highlights
Development of integrated circuits (IC) along Moore’s law has brought the technology to a level where the smallest features of semiconductor devices are smaller than 10 nm
While significant progress has been made in resolution with multiple patterning techniques and extreme ultraviolet lithography, several masks and lithography cycles are needed for each layer, and alignment errors between subsequent patterning steps increase significantly as the device structures get smaller [1,2]
Lithography tools are the most expensive ones in semiconductor fabrication yet are prone to costly errors
Summary
Development of integrated circuits (IC) along Moore’s law has brought the technology to a level where the smallest features of semiconductor devices are smaller than 10 nm. There is an urgent need to replace, or at least, simplify as many lithography process steps as possible with self-aligning thin film fabrication processes, especially at the smallest and most critical dimensions for alignment This has been attempted and realized with varying levels of success by area-selective thin film deposition methods, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD) [3,4,5,6,7,8]. It has been noted that when applied as shown, the polymer and the subsequently deposited film, if any, exactly copy the original pattern If this is not desired, selected areas must be covered by a blocking layer or resist either before or after the self-aligned polymer etching process.
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