Self-aligned bottom-gate submicrometer-channel-length a-Si-:H thin-film transistors

Abstract

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 mu m are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 mu m. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10- mu m device and 140% for a 1- mu m device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 mu m. Current on/off ratios taken at V/sub d/=5 V and V/sub G/=15 V and 0 V, respectively, are approximately 1*10/sup 6/ for the 1- and 12- mu m-long devices. The on/off ratio is reduced to 1*10/sup 5/ for the 0.4- mu m device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>