Selection of area-time efficient custom instructions for FPGA realization

Abstract

Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. In this paper, we propose a framework for reconfigurable processors that can rapidly identify a reduced set of profitable custom instructions and their area-time costs without the need for actual hardware synthesis. The framework relies on a strategy to rapidly estimate the utilization of the LUT (look-up table) based FPGAs (field programmable gate arrays) for the custom instructions. Simulations based on applications from benchmark suites show that an average area reduction of over 40% can be achieved with only an average performance loss of less than 2% by selecting a reduced set of custom instructions with the proposed framework. In addition, we show that the proposed framework can lead to an average performance gain of over 40% and an average area reduction of over 32% when compared to an approach that exploits the regularity of the custom instruction data-paths for area-efficient realizations.