Seiba: An FPGA Overlay-Based Approach to Rapid Application Development

Abstract

Although high-level synthesis (HLS) improves designer productivity through abstraction, FPGA high-level synthesis stills suffers from lengthy compilation that limits the number of design iterations a developer can achieve per day. One method of minimizing these compile times is compiling designs with innate programmability, aka FPGA overlays, and using their runtime configuration to implement functional changes, as opposed to recompiling the design. In this paper, we introduce Seiba, an application development approach that integrates HLS circuits with FPGA overlays to create reconfigurable platforms that are rapidly configured to reduce development time. As a dual-layer compilation approach, Seiba enables users to choose an appropriate tradeoff between productivity and overhead by implementing incremental changes quickly through overlay configuration or efficiently through FPGA recompilation. To handle this integration, our approach uses a novel overlay architecture that offers flexible overlay configuration which can “patch” and redirect execution from an application circuit to runtime configurable overlay functional units. Our results show that by leveraging the overlay's runtime configurability, our development flow can significantly reduce the number of FPGA compilations in a development cycle.