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Abstract
This paper presents experimental Single Event Gate Rupture (SEGR) data for Metal-Insulator-Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross-section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed.
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