SEE-Hardened-by-Design Area-Efficient SRAMs

Abstract

With the advent of error detection and correction (EDAC) schemes for SRAMs, the reliability of SRAMs in radiation environments has improved. However, there are several problems that still need to be addressed. In particular, single-event-transient (SET) hardening of peripheral circuitry, including row and column decoders, sense amplifiers, as well as the EDAC circuitry itself, has not been adequately addressed. We have designed a self-scrubbing, multi-bank SRAM with EDAC that corrects single-bit errors without redundancy in the memory cells, with no downtime. Access times are only a single gate delay more than an unhardened SRAM. Furthermore, the peripheral circuitry is hardened with respect to single-event transients. The area overhead for this SET hardening is a constant, independent of the number of bits in the SRAM. We have designed SRAMs based on three different types of memory cells: 1) the six-transistor (6T) SRAM cell, 2) a one-transistor, one-capacitor (1T1C) DRAM cell, and 3) a single (edgeless) transistor (1T) DRAM cell. We have demonstrated that the soft-error rate for our memories is well under 10 -10 errors per bit per day, for all three types of memory cells. The area per memory cell is about 3X smaller for the 1T1C compared to the 6T, while the area per memory cell is about 2X smaller for the 1T versus the 6T. All three designs employ minimum area memory cells.