Seedless Cu Electroplating on Co-W Thin Films in Low pH Electrolyte: Early Stages of Formation.

Rúben F Santos,Filomena Viana,Bruno M C Oliveira,Alexandre Chícharo,Manuel F Vieira,Sónia Simões,Paulo J Ferreira,Pedro Alpuim

doi:10.3390/nano11081914

Abstract

The use of Ta/TaN barrier bilayer systems in electronic applications has been ubiquitous over the last decade. Alternative materials such as Co-W or Ru-W alloys have gathered interest as possible replacements due to their conjugation of favourable electrical properties and barrier layer efficiency at reduced thicknesses while enabling seedless Cu electroplating. The microstructure, morphology, and electrical properties of Cu films directly electrodeposited onto Co-W or Ru-W are important to assess, concomitant with their ability to withstand the electroplating baths/conditions. This work investigates the effects of the current application method and pH value of the electroplating solution on the electrocrystallisation behaviour of Cu deposited onto a Co-W barrier layer. The film structure, morphology, and chemical composition were studied by X-ray diffraction, scanning electron microscopy and atomic force microscopy, as well as photoelectron spectroscopy. The results show that the electrolyte solution at pH 1.8 is incapable of creating a compact Cu film over the Co-W layer in either pulsed or direct-current modes. At higher pH, a continuous film is formed. A mechanism is proposed for the nucleation and growth of Cu on Co-W, where a balance between Cu nucleation, growth, and preferential Co dissolution dictates the substrate area coverage and compactness of the electrodeposited films.

Highlights

Following the trend established by Moore’s Law, more transistors are being packed in a single chip as the dimensions continue to downscale
Electroless methods used for the synthesis of Co-W-based thin films have been reported in the literature [16,17,18], but the direct electroplating of Cu on Co-W-based thin films is frankly unaddressed
The feasibility of Co-W as a directly electroplatable diffusion barrier layer to interconnect metallisation depends on its capability to grow a Cu film on top, with adequate morphological and microstructural characteristics and equivalent or superior electronic performance to conventional barrier layer systems

Summary

Introduction

Following the trend established by Moore’s Law, more transistors are being packed in a single chip as the dimensions continue to downscale. As of 2020, the transistor count is on the order of several tens of billions in CPU and GPU systems This continuous miniaturisation makes the massive spread of electronic devices, computers, smartphones, and wearables possible, which is followed by great manufacturing challenges, where conventional processes and materials are reaching their usability limits and requiring either an improvement or replacement. In this regard, copper interconnects, which act as electrical paths in integrated circuits, have been downscaled, thereby experiencing a reduction in width and thickness.

Methods

Results

Conclusion