Seed layer engineering for crack-free sol–gel Alumina deposition on GFETs

Abstract

Low-cost and low thermal budget-based spin-coated sol–gel Alumina was explored as a dielectric/passivation layer for graphene field effect transistor (GFET). Post thermal annealing, the crack was observed in the sol–gel Alumina layer exactly above the graphene channel. The possible mechanism of crack could be graphene lateral restoring movement due to (i) the Thermal Expansion Coefficient (TEC) difference between graphene and adjacent layers and (ii) shrinkage stress generated during the solvent removal process. Based on the crack formation phenomenon, a combination of different annealing schemes (low thermal budget deep ultraviolet (DUV) annealing) and seed layer engineering (thickness and different deposition schemes) were carried out. Finally, a novel two-step seed layer deposition method with DUV annealing was proposed and demonstrated to resolve the crack issue successfully and also able to retain the Dirac point in the electrical characteristics.