Seed Layer and Multistack Approaches to Reduce Leakage in SrTiO3-Based Metal–Insulator–Metal Capacitors Using TiN Bottom Electrode

Abstract

Leakage reduction is crucial for metal–insulator–metal (MIM) capacitors for future dynamic random access memory (DRAM) nodes. In previous investigations we showed that increasing the Sr-content would result in leakage reduction of SrTiO3 (STO) films deposited on TiN. [1,2] In this work we demonstrate for thin (10 nm) stoichiometric SrTiO3 films that the leakage properties can be significantly lowered (while keeping high capacitance densities) by using stacking approaches such as seed layer (thin STO layer crystallized before the “bulk” STO deposition) and multistack SrTiO3/GdAlO3/SrTiO3. In this work, SrTiO3 films are deposited using a low temperature ALD process enabling the use of low-cost, manufacturable-friendly TiN-bottom electrode.