SEE vulnerability bit analysis method for switch matrix of SRAM-based FPGA circuits

Abstract

Analytical method is becoming a novel and attractive method to evaluate the Single Event Effect (SEE) performance of the circuit implemented in SRAM-based FPGA. A SEE vulnerability analysis model of FPGA circuit is proposed, which describes the function between the soft failure rate and the SEE vulnerability bit of FPGA circuit. The analysis methodology of SEE vulnerability bit of switch matrix is stated, and a software based on RapidSmith platform is developed. Fault injection based on reconfiguration of SRAM-based FPGA has been developed to verify the analysis method. The experimental results indicate that the SEE vulnerability bit analysis method is feasible.