Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks

Abstract

Research explorations in new devices, new architectures and algorithms are being performed to reduce leakage power dissipation. As a solution to reduce the leakage power in CMOS based designs, Magnetic Tunnel Junction (MTJ) devices are being investigated to design MTJ/CMOS Logic-In-Memory (LIM) circuits. The MTJ/CMOS circuits have advantages such as near-zero leakage power and non-volatility which make them useful to design sudden power-outage resilient non-volatile processors. However, the security of the existing MTJ/CMOS circuits against power analysis based side-channel attacks need to be evaluated before deploying these circuits in real world applications. Therefore, in this paper, we are performing the security evaluation of the existing MTJ/CMOS circuits against power analysis attacks for the first time in the literature. From the simulations, it is shown that the existing MTJ/CMOS circuits consume high current during the switching of MTJs thereby leaking the information and becoming vulnerable to power analysis based attacks. Further, to thwart power analysis attacks in MTJ/CMOS circuits, we propose a novel secure MTJ/CMOS logic (SMCL) which consumes uniform current irrespective of switching of MTJs. Simulations are performed using 45nm CMOS technology with perpendicular anisotropy CoFeB/MgO MTJ model using Cadence Spectre simulator. Calculated values of Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) show that the proposed SMCLL gates consume uniform energy for every cycle of operation irrespective of their input transition. The uniform energy rate and low power operation shows that the proposed SMCL gates are energy-efficient in nature and resistant to power analysis attacks.