Security Analysis of Delay-Based Strong PUFs with Multiple Delay Lines

Abstract

Using a novel circuit design, we investigate if the modeling- resistance of delay-based, CMOS-compatible strong PUFs can be increased by the usage of multiple delay lines. Studying a circuit inspired by the Arbiter PUF, but using four instead of merely two delay lines, we obtain evidence showing that the usage of many delay lines does not significantly increase the security of the strong PUF circuit. Based on our findings, we suggest future research directions.