Search algorithm of write voltage optimization in NAND flash memory

Abstract

In NAND flash memory, the major problem is voltage immigration which is the result of program and erase (PE) cycling number and data retention time. Although previous works study the write voltage optimization for NAND flash memory, the write voltage optimization of multilevel coding (MLC) and bit-interleaved coded modulation (BICM) structure have not been focused, therefore, in this work, we propose the search algorithm of write voltage optimization for MLC and BICM structure. The search algorithm can reduce the number of possible write voltages and provides the optimal write voltage for each PE cycling number. The bit-error rate (BER) performance of optimized write voltage is lower than the fixed write voltage in BICM structure. Moreover, the proposed optimization technique provides the most significant bit (MSB) and least significant bit (LSB) of MLC structure with identical BER performances.