Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications

Abstract

Shift-add/subtract circuits constitute the basic building blocks of several frequently used complex arithmetic units such as multiple constant multipliers, exponentiation circuits, fast division circuits, CORDIC rotators, logarithmic and residue number conversation units, etc. Fine-grained pipelined designs of these arithmetic units have strong potential to improve the power-performance-reliability profile of several compute-intensive and constraint-driven applications like digital signal processing, cryptography, and communication. Efficient pipelining of these circuits therefore requires precise analysis of propagation delay of its basic blocks like shift-add/subtract circuits and connected shift-add arrays. Moreover, careful pipelining of shift-add/subtract circuits has strong potential to enhance the throughput of complex arithmetic units where they are embodied. In this paper, we derive seamlessly pipelined shift-add/subtract circuits to achieve a desired critical path delay based on the throughput requirement of the embodying arithmetic units and application environment. We aim at providing a brief demonstration of how the pipelined shift-add/subtract circuits could used to enhance the performance and reduce power consumption of some typical constraint-driven computations. It has been observed that shift-add based logarithmic/antilogarithmic converters achieve area-efficient and high-performance inter-conversion between binary numbers and logarithmic numbers with low approximation errors to be used efficiently for logarithmic number system (LNS)-based computations. In this paper, we show that the use of seamlessly pipelined shift-adds/subtract circuits provide remarkable improvement of logarithmic/antilogarithmic converters over the conventional ones, and can be used in the LNS-based computing system to boost the performance and reduce the overall energy consumption. We have also shown how throughput rate of high-precision exponentiation circuits can be enhanced by seamlessly pipelined shift-add circuits for cryptographic applications.