Scratch-pad memory banking for energy reduction in embedded signal processing systems

Abstract

Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects - namely power consumption, performance, and chip area - are heavily influenced, if not dominated, by the data transfer and storage aspects. In such applications, hierarchical memory organizations reduce energy consumption by exploiting the nonuniformity of memory accesses and assigning the frequentlyaccessed data to low levels of the hierarchy. Moreover, within a given level, power can be reduced by memory partitioning - whose principle is to divide the address space in several smaller blocks, and to map these blocks to physical memory banks. This paper addresses the problem of energy-aware banking of on-chip memories for data-intensive applications, proposing a technique that is guided by the intensity of memory accesses within the array space of signals.