Scratching by pad asperities in copper electrochemical-mechanical polishing

Abstract

Low dielectric constant materials/Cu interconnects integration technology provides the direction as well as the challenges in the fabrication of integrated circuits (IC) wafers during copper electrochemical-mechanical polishing (ECMP). These challenges arise primarily from the mechanical fragility of such dielectrics, in which the undesirable scratches are prone to produce. To mitigate this problem, a new model is proposed to predict the initiation of scratching based on the mechanical properties of passive layer and copper substrate. In order to deduce the ratio of the passive layer yield strength to the substrate yield strength and the layer thickness, the limit analysis solution of surface scratch under Berkovich indenter is used to analyze the nano-scratch experimental measurements. The modulus of the passive layer can be calculated by the nano-indentation test combined with the FEM simulation. It is found that the film modulus is about 30% of the substrate modulus. Various regimes of scratching are delineated by FEM modeling and the results are verified by experimental data.