Scheduling with register constraints for DSP architectures

Abstract

In recent years, architectural synthesis techniques for real-time signal processing applications have been given much attention. Optimization techniques have been developed which aim at minimizing the chip area for a given throughput. Especially for low to medium throughput applications, one can witness a growing use of embedded programmable architectures, referred to as “ ASIPs”. ASIPs offer programmability and components re-use, which allows to reduce the time-to-market. ASIPs typically have an irregular parallel architecture, with distributed register structures. The data path may contain several special-purpose register-files, of which the number of registers is sometimes parameterizable. New retargetable code generation techniques are needed to generate high-quality machine code for ASIPs. During this process, a close interaction between scheduling and register allocation is essential. This paper addresses the problem of scheduling with tight register constraints. A new technique for calculating the maximum number of live signals is proposed. It is based on retiming, and it is used to reduce the register cost of the design below a user-specified constraint. This new approach has been successfully applied to a number of real-life applications.