Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

Abstract

Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.