Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin

Abstract

Post-Silicon clock-Skew Tuning (PSST) is a promising technology for improving performance-yield of VLSIs under process variations. On the other hand, the resultant circuit after PSST should be also robust for run-time timing variations due to the change of temperature, power supply noise, etc. So, post-silicon skew tuning problem considering timing margin arises. In this work, the timing margin in the context of PSST is defined in terms of control values for programmable delay elements (PDEs), and a novel PDE tuning algorithm considering timing margin is proposed. The key component of our PDE tuning procedure is a timing test considering timing margin, in which we need to use a set of different PDE settings (mu-margin PDE test-settings) from a designed (target) PDE setting. Discussions done in this work are devoted to reducing test cost in terms of the number of timing test as well as PDE setting cost in terms of the number of mu-margin PDE test-settings.