Scarce-State-Transition Viterbi Decoding of Punctured Convolutional Codes for VLSI Implementation

Abstract

In Viterbi decoding of (n, k) convolutional codes of total encoder memory M, the decoder carries out (2 k -l)-ary comparisons at each node of the 2 M -state encoder trellis [1, 2]. Recently, Kubota et al. [3] and others [4-6] proposed scarce-state-transition (SST) type register-exchange (information bits are associated with surviving paths) Viterbi decoding system of convolutional codes, implemented on CMOS VLSI chips. At an information rate of 25 Mbit/s and a bit-error-rate (BER) of 0.0001, a power consumption reduction of 40% can be achieved by the system when compared with a hypothetical register-exchange type of Viterbi decoder. The measured power consumption with increasing channel noise was also reported in [6] and the technique was proposed for mobile communication channels [7]. For high-rate, powerful codes, the implementation of the Viterbi decoder becomes impractical. In a recent paper, Lee et al. [8] proposed SST-type syndrome-former error-trellis decoding of high rate-(n - 1)/n convolutional codes. The number of comparisons at each trellis node of the decoding process is reduced to at most a binary comparison but the number of trellis states is doubled. The increase in trellis states makes the decoding technique less attractive for practical implementation. In 1979, Cain et al. [9] showed that the Viterbi decoding of high-rate convolutional codes can be significantly simplified by employing punctured convolutional codes. The punctured convolutional codes are obtained by periodically perforating coded symbols from the output of a low-rate R=1/n convolutional code, called the mother code, and the decoding complexity is hardly more complex than decoding the low-rate code.