Scan-chain masking technique for low power circuit testing

Abstract

This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This, though reduce dynamic power significantly; can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using genetic algorithm and use it properly so that both dynamic and leakage power are reduced. The average improvement in dynamic power is 20.4% and for leakage power it is about 10.8% (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.