Scan chain configuration based X-filling for low power and high quality testing

Abstract

Test power is a serious problem in the scan-based testing. DFT-based techniques and X-filling are two effective ways to reduce both shift power and capture power. However, few of the previous methods pay attention to the defect coverage when reducing the test power. Many of them, especially for X-filling methods, may lead to low defect coverage. In this paper, based on an effective scan chain configuration, we present a segment-based X-filling to reduce test power and keep the defect coverage. The scan chain configuration tries to cluster the scan flip-flops with common successors into one scan chain, in order to distribute the specified bits per pattern over a minimum number of chains. Based on the configuration, all the bits to some scan chains in a vector may be don't care(X). For these scan chains, segment-based X-filling is used to reduce test power and keep the defect coverage. Compared with the ordinary full-scan architecture, experimental results show that low test power and high defect coverage can be achieved.