Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs

Abstract

2.5-D integration is emerging as the precursor to stacked 3-D ICs. Since the silicon interposer and micro-bumps in 2.5-D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 standard. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay defects in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. The proposed test technique is fully compatible with the IEEE 1149.1 architecture and can be controlled by the test-access port controller. We present HSPICE and ModelSim simulation results to demonstrate the effectiveness of fault detection. Simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach. We also present synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 standard. Synthesis results show that the cost of implementation of the architecture is negligible.