Abstract
When scaling a trench capacitor cell developed for the 4Mbit DRAM further down, both process and device limits are encountered. Device related topics are the subject of this paper. Issues to be discussed are: (1) narrow width effects of pass transistors, (2) short channel effects, (3) effect of storage region on pass transistor, (4) isolation between neighbouring cells.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
