Scaling trends in energy recovery logic: an analytical approach

Abstract

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.