Scaling the Damascene-Metal-Gate integration process via electron beam lithography

Abstract

Damascene-metal-gate technology gives rise to the implementation of crystalline gate dielectrics into modern MOS devices. Evaluation of the scalability of this fabrication process is important for a subsequent use in industrial-scale fabrication. Devices were processed on ultrathin Unibond SOI-Wafers. A high-K specially designed layout was patterned onto the substrates via mix and match electron-beam / UV lithography. A gate length of ~100 nm was chosen for a first approach. Reactive ion etching was performed for dummy gate and active area formation. Subsequently the surface was planarized via chemical mechanical planarization (CMP). In the following the dummy gate was removed, and in one case replaced with molecular beam epitaxially grown crystalline gadolinium oxide (Gd <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) and on the other case with thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as reference material. Palladium was used as source/drain- and gate-metallisation. Atomic force microscopy and scanning electron microscopy were carried out for process monitoring. Especially the dummy gate formation, subsequent CMP and cleaning processes, as well as the dummy gate removal and the conformity of the replacement gate stack are of particular interest.