Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS processes

Abstract

This paper examines the implications of scaling an n-type bulk-driven MOSFET into the 90 nm node in an effort to make the device suitable for analog designs operating at 0.7 V, the minimum supply voltage predicted for the end of bulk CMOS. Observations will suggest that process scaling has caused the g mb / g m ratio to degrade from 0.38 to 0.12 between representative 0.25 μm and 65 nm technologies and that the benefits expected from traditional bulk-driven circuit architectures are no longer present in deca-nanometer processes unless certain modifications are considered. Furthermore, it will be shown that the major disadvantages of the bulk-driven MOSFET – i.e., its low intrinsic gain, low cut-off frequency and layout area requirements – can be improved by as much as 110%, 50% and 53%, respectively, if delta doping (defined as a heavily-doped buried layer of 100 nm thickness) and deep trench isolation are used instead of conventional uniform doping and triple-well isolation.