Scaling Rules for the Energy of Decoder Circuits

Abstract

A standard VLSI model is used to derive universal lower bounds on the energy of decoder circuits. In the circuit model used, the product of the circuit area and number of clock cycles, or the area-time complexity is proportional to the energy of computation. Lower bounds as a function of block length n are presented for three different circuit paradigms. Firstly, for circuits that compute in parallel, an Ω(n(logn)1/2) scaling rule is shown. Secondly, for circuits that compute serially, an Ω(nlogn) lower bound is presented. Thirdly, for a sequence of decoding circuits in which the number of output pins grows arbitrarily with block length, the energy is shown to grow as Ω(n(logn)1/5). In addition, it is shown that the energy complexity of almost all LDPC decoders that can get close to capacity and whose Tanner graphs are generated according to a uniform standard configuration model must take Ω(n2) area to implement directly.