Scaling properties of bipolar devices

Abstract

The procedures for optimizing the vertical doping profile of bipolar transistors and for scaling bipolar switching circuits are discussed. A bipolar circuit remains optimized for power-delay operation in scaling if the relative contributions to the circuit delay of every capacitance and resistance component of the circuit are kept constant. This condition is realized only by coordinated reductions of both the vertical doping profiles and the horizontal dimensions and appropiately varying the current. As the base width is reduced in scaling, the emitter depth must be reduced proportionately to maintain base width control and reproducibility, and the base doping must be increased to avoid punch through. For emitters less than 200nm deep, the current gain is no longer determined by the base sheet resistance alone, but depends strongly on the emitter contact technology. Also, for base doping greater than about 5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , the effects of heavy doping in the base region as well as in the emitter region become important in determining the device characteristics.