Scaling of metal gate workfunction variability in nanometer SOI-FinFETs

Abstract

A work function variability caused by the metal gate is studied in a 10.7 nm gate length SOI-FinFET in the sub-threshold region at low drain bias using 3D quantum corrected finite element (FE) drift-diffusion (DD) simulations. The variability is compared with that observed in a 25 nm gate length SOI-FinFET. The 3D DD simulations are meticulously calibrated against 3D FE ensemble Monte Carlo simulations with Schrödinger equation based quantum corrections. The calibration adjusted the material parameters that define the mobility model and the density gradient corrections. For the 10.7 nm gate length device, σ(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) ranges between 17.8 mV, when the grain size is 10 nm, to 52.2 mV, when the grain size is 3 nm. The SS is less sensitive to variations in the metal grain size (10 nm-3 nm) than in the corresponding 25 nm gate length device. We have also found that the 10.7 nm device shows similarities with a bimodal distribution for both threshold voltage and off current when the grain size is 10 nm due to a large size of the grains compared to the gate.