Scaling of InGaAs MOSFETs into deep-submicron regime (invited)

Abstract

We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> exceeding 1.1 mS/μm. Oxide thickness scaling is performed to improve the on-state/off-state performance and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> is further improved to 1.3 mS/μm. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to steadily improve high-k/InGaAs interface quality and on-state/off-state performance of the devices. We have also demonstrated the first well-behaved inversion-mode InGaAs FinFET with ALD Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as gate dielectric using novel damage-free etching techniques. Detailed analysis of SS, DIBL and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> roll-off are carried out on FinFETs with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> down to 100 nm and W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin</sub> down to 40 nm. The short-channel effect (SCE) of planar InGaAs MOSFETs is greatly improved by the 3D structure design. The result confirms that the newly developed dry/wet etching process produces damage-free InGaAs sidewalls and the high-k/3D InGaAs interface is comparable to the 2D case. Finally, ultra-shallow doping for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> adjustment in deep submicron InGaAs MOSFETs using sulfur monolayers is demonstrated. This brings new potential solution to ultra-shallow junction formation for the further scaling of III-V MOSFETs.