Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

R Coquand,M Casse,S Barraud,V Maffini-Alvaro,E Ernst,D Munteanu,P Leroux,T Poiroux,S Monfray,M.-P Samson,F Boeuf,G Ghibaudo,C Tabone,P Perreau,C Vizioz,C Comboroure,S Barnola

doi:10.1109/ulis.2012.6193351

Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

R Coquand, M Casse + Show 15 more

https://doi.org/10.1109/ulis.2012.6193351

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Publication Date: Mar 1, 2012

Citations: 40

Affiliation: Atomic Energy and Alternative Energies Commission, CEA LETI, Université Grenoble Alpes, Grenoble Institute of Technology, CEA Grenoble, STMicroelectronics (France), Institut de Microélectronique, Electromagnétisme et Photonique, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence, French National Centre for Scientific Research

#Tri-Gate Nanowire #Nanowire Width + Show 8 more

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Abstract

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

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