Abstract
Six-band kmiddotp Monte Carlo device simulation is used to estimate the drain current enhancements in (110) surface and in uniaxially compressively stressed bulk pMOSFETs for gate lengths down to 30 nm. Satisfactory agreement is found with measured long-channel mobility enhancements as a function of the channel direction for (110) surface orientation or as a function of stress. It turns out that the stress-induced current improvement becomes larger than for the unstrained-Si (110) surface orientation at stress levels above 1 GPa. Specifically, for a gate length of 45 nm, the on-current enhancement is 50% for 1.5 GPa compared to 35% for the favorable lang-110rang channel direction in a (110) pMOSFET
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