Scaling Modular Exponentiation Hardware to the Minimum

Abstract

This paper introduces a novel hardware architecture for modular exponentiation. The proposed architecture is optimised for circuit area sensitive applications such as resource-constrained mobile devices in ubiquitous computing. The architecture provides a scalable design suitable for both the RSA and Diffie-Hellman cryptosystems. This architecture has been implemented on UMC 0.13μm CMOS standard cell technology. The 1,024-bit design utilises only 3,188 gates and 3,072 RAM bits. The 2,048-bit design consumes only 4,275 gates and 6,144 RAM bits. To the authors' knowledge, the proposed architecture achieves the smallest area in comparison to other candidates reported in the literature. The 1,024-bit design reports the lowest power consumption of 0.31mW@50MHz. (5 pages)