Scaling down the supply voltage of CPL circuits

Abstract

Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates CPL (Complementary Pass-Transistor Logic) circuits operating on near-threshold regions in terms of low EDP. All circuits are simulated with HSPICE at a PTM 0.13μm CMOS technology by varying supply voltages from 0.6V to 1.2V with 0.1V steps. The results demonstrate that lowering supply voltage of the CPL circuits is advantageous especially in medium-voltage regions (700mv-800mv), which yield the best EDP.