Scaling Beyond 7nm Node: An Overview of Gate-All-Around FETs

Abstract

Gate-all-around (GAA) is a promising MOSFET structure to continue scaling down the size of CMOS devices beyond 7 nm technology node. This paper gives an overview of different types of GAAFETs including lateral and vertical channel orientations, and nanowire (NW) and nanosheet (NSH) channel structures. The advantages and disadvantages of these structures are discussed. Besides, key parameters such as gate length, transfer characteristics, drain-induced barrier lowering (DIBL), subthreshold slop (SS), and threshold voltage are used to compare the electrical performance of different structures. The review summarizes the advantages of four structures: first, the lateral nanowire tends to have the lowest simulated DIBL (45mV/V) and SS (68mV/dec) due to the circular shape of the channel structure. Second, the lateral nanosheet has a higher driving current or on-state current (Ion = 85μA) than nanowire due to large effective width, Weff. Third, the vertical cylindrical is relaxed on the gate length and contacted gate pitch and has the potential to reduce short channel effects (SCEs) by reducing the diameter of the nanowire. Last, the cylindrical junctionless structure has the lowest Ioff and threshold voltage roll-off which is suitable for low power electronics, and it is easier for fabrication.