Scaling behaviors of silicon-nitride layer for charge-trapping memory

Abstract

The authors investigate the scaling behaviors of a silicon-nitride layer for use in a charge-trapping memory device according to dimension downscaling of the memory-device cells. As is known, charge storage takes place in discrete traps in the silicon-nitride layer. In this study, a 5-nm-thick charge-storage layer in the conventional oxide-nitride-oxide device is investigated and shows considerable trap-based memory characteristics, but encounters a retention problem. Therefore, they adopt a modulated tunnel barrier to replace the single tunnel oxide so as to improve the charge-retention property. As a result, experimental results show excellent memory program/erase operation behaviors and indicate further scalability of the charge-storage layer compared to the conventional oxide-nitride-oxide device.