Abstract
A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 μm; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 μm, TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I/sub OFF/=1 nA/μm for nMOS and pMOS, respectively).
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
