Scalable Spice Modeling of Integrated Power LDMOS Device Using a Cell-Based Building Block Approach

Abstract

This paper illustrates a scalable Spice modeling method for an integrated power LDMOS device based on a multi-cell array structure. Depending on the location in the array (corner, edge, inner), three different types of cells were identified to have distinct electrical characteristics. Each cell type was modeled independently and was treated as a building block for the final scalable model. The three building block models could be relatively accurately generated because they were required to fit only one cell with fixed channel length and width. By combining the three building blocks, a scalable Spice model was created.