Scalable pipelined CORDIC architecture design and implementation in FPGA

Abstract

In Digital Signal Processing, trigonometry and complex multiplications are used in many signal equations, such as synchronization and equalization. Therefore, a fast and an efficient method to calculate trigonometry and complex multiplications are required. Coordinate Rotation Digital Computer (CORDIC) is trigonometric algorithm [1] that is used to transforming data from rectangular to polar and vice versa. CORDIC also can be used other to compute several trigonometry functions, either directly or indirectly [1]. The proposed CORDIC design is based on Pipeline datapath Architecture. By using pipeline architecture, the design is able to calculate continuous input, has high throughput, and doesn't need ROM or registers to save constant angle iteration of CORDIC. The design process is started by modelling CORDIC function, design datapath and control unit, coding to hardware description language using Verilog HDL, synthesized using Quartus II Version 7.2 and implemented on ALTERA Cyclone II DE2 EP2C35F672C6N FPGA. Synthesis result shows that the design is able to work at 81.31 MHz.