Abstract
Thermal budget, stack thickness, and dipolar offset field control are crucial for seamless integration of perpendicular magnetic junctions (pMTJ) into semiconductor integrated circuits to build scalable spin-transfer-torque magnetoresistive random access memory. This paper is concerned with materials and process tuning to deliver thermally robust (400 °C, 30 min) and thin (i.e., fewer layers and integration-friendly) pMTJ utilizing Co/Pt-based bottom pinned layers. Interlayer roughness control is identified as a key enabler to achieve high thermal budgets. The dipolar offset fields of the developed film stacks at scaled dimensions are evaluated by micromagnetic simulations. This paper shows a path towards achieving sub-15 nm-thick pMTJ with tunneling magnetoresistance ratio higher than 150% after 30 min of thermal excursion at 400 °C.
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