SAT-based state encoding for peak current Minimization

Abstract

As the silicon process technology advances, chip reliability becomes more and more important. One of the critical factors that affect the chip reliability is the peak current in the circuit. In particular, high current peaks at the time of state transition in synchronous finite state machine (FSM) circuits often make the circuits very unstable in execution. This work addresses the state encoding problem with the objective of minimizing peak current in FSMs. Unlike the previous poweraware state encoding algorithms, where the primary objective is to reduce the amount of switching activities of state register and the problem of reducing peak current has not been addressed at all or considered as a secondary objective, which obviously severely limits the search space of state encoding for minimizing peak current, the proposed algorithm, called SAT-pc, places the importance on the reliability, i.e., peak current. Specifically, we solve two important state encoding problems in two phases: (Phase 1) we present an optimal solution to the problem of state encoding for directly minimizing peak current, by formulating it into the SAT problem with pseudo-Boolean expressions, which leads to a full exploration of the search space; (Phase 2) we then propose an efficient SAT-based heuristic to solve the state re-encoding problem for minimizing switching power without deteriorating the minimum peak current obtained in Phase 1. Through an experimentation using MCNC benchmarks, it is shown that SAT-pc is able to reduce the peak current by 47% and 28%, compared to POW3[4] that minimizes the switching power only and POW3[4] + [7] that minimizes the switching power and then peak current, respectively.