SAT: Switchable Address Translation for Flash Memory Storages

Abstract

NAND flash-based storage systems such as solid-state disk (SSDs) are becoming an alternative secondary storage solution for various applications. In flash-based storage systems, an intermediate software layer called a flash translation layer (FTL) is usually employed to hide the erase-before-write characteristics of the NAND flash memory. In FTL schemes, garbage collection is the major factor limiting the performance of the storage device. In this paper, we propose a new hybrid-level FTL scheme called switchable address translation (SAT), which dynamically switches the address mapping scheme according to the access pattern and the memory usage of the mapping tables. In order to minimize the garbage collection overhead, SAT removes the merge operation which is an innate problem of legacy hybrid-level FTL schemes. Further, unlike previous schemes, SAT utilizes free blocks and controls the execution of garbage collection. Our experimental results show that the proposed SAT scheme reduces the garbage collection overhead significantly as compared to the existing FTL schemes.