Abstract
Logic locking (LL) is used to protect designs from various security vulnerabilities in the Integrated Circuits (IC) supply chain. Development of a satisfiability checking (SAT) attack in 2015, which breaks all the existing LL techniques at that time, divides the LL defenses into two classes: pre-SAT and post-SAT. Even though the SAT attack is powerful in breaking circuits locked with high output corruptibility LL techniques, it fails to work in compound LL circuits where both high output corruptibility and low output corruptibility locking techniques are used. In this work, we propose a SAT based method capable of partially decrypting the high output corruptibility keys when more than one LL technique is used to lock the circuit functionality. This partial decryption of a significant number of key bits exposes the security vulnerability of the compound LL technique and it helps the attacker to use this as a pre-processing step for more advanced attacks or brute-force on the remaining key bits to extract the exact netlist. Experiments of CSAW Logic Locking Conquest 2019 challenge benchmarks show the usefulness of our method.
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