Abstract
This paper deals with the development of SARMOS process for the fabrication of field-effect transistors. In this process an RF sputter deposited molybdenum film is used as the gate and the source drain windows are sputter etched to obtain a short gate length combined with pyrolytically deposited doped oxide diffusion technology. The p-channel MOS-FETs fabricated on <111> phosphorous doped n-type silicon with resistivity in the range of 3–6 ohm-cm and a channel length of 8 μm had an apparent threshold voltage of 2. 5 volts (10 μ criterion) and drain-to-source breakdown voltage of 30 volts.
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