Sampling for Cache and Processor Simulation

Abstract

There are a wealth of technological alternatives that can be incorporated into a cache or processor design. The memory configuration and the cache size, associativity and block size for each of the components in the heirarchy are some of these applicable to memory subsystems. For processors, these include branch handling strategies, functional unit duplication, and instruction fetch, issue, completion and retirement policies. The deciding factor between the various choices available is a function of the performance each adds, versus the cost each incurs. The large amount of available design choices inflates the design space. The profitability of a given design is measured through the excution of application programs and other workloads. Trace-driven simulation is used to simplify this process.